The present invention relates to a method and apparatus for controlling the read clock signal rate of a First-In First-Out (FIFO) data memory. The invention relates particularly, but not exclusively, to the desynchronisation, or demapping, of plesiochronous data elements from a Synchronous transmission format, in a telecommunications network system.
It is well known to use a FIFO data memory, or buffer (hereinafter referred to as a FIFO), in the synchronisation, or desynchronisation, of data. For example, FIFOs are commonly used as an interface between two digital systems to compensate for variations in the rate at which data is required, or produced, by one or both of the systems.
In many applications, particularly telecommunications applications, the data-read from the FIFO must conform to one or more industry standards as laid down by, for example, the American National Standards Institute (ANSI) or the International Telecommunications Union Telecommunications Standardisation Sector (ITU-T). In particular, standards or specifications are laid down concerning the smoothness of the produced data stream. Smoothness is typically measured in terms of xe2x80x98jitterxe2x80x99 or xe2x80x98wanderxe2x80x99 which are a common measure of how accurately the data rate or frequency conforms to a given standard.
It is known to employ a phase-locked loop (PLL) controller to control the rate at which data is read from a FIFO, and hence to control the smoothness of the produced output data stream. Conventionally, the PLL controller is implemented in hardware and comprises a voltage controlled oscillator coupled with an analogue filter in conventional manner. Not only must such controllers meet the applicable wander and jitter specifications during normal operating conditions, but they must also react quickly enough to prevent FIFO overflow or underflow in extreme operating conditions. It is found that conventional controllers are unable to meet the exacting standards which are demanded in modern applications, particularly in the telecommunications industry.
For example, in a synchronous transmission telecommunications network, such as a Synchronous Digital Hierarchy (SDH) or SONET network, it is often necessary to transmit plesiochronous data elements, or plesiochronous Digital Hierarchy (PDH) data elements, in accordance with the SDH data framing structure. To this end, each PDH data element is appended with control information, known as path overhead, to produce a corresponding SDH data element, known as a virtual container. A FIFO is normally used in the recovery or demapping of the PDH data elements from the SDH data elements. Typically, an input data stream comprising PDH data elements encoded in an SDH data framing structure is provided to a desynchronising apparatus, which includes a FIFO, and an output data stream is produced which comprises the decoded PDH data elements. Before each data element is fed to the FIFO, the path overhead is removed thereby creating gaps in the data stream. Thus, data is written to the FIFO at a non-uniform rate. Further, the rate at which data is written to the FIFO may vary as a result of pointer movements and mapping bits which are intrinsic in SDH systems.
The rate at which data is read out of the FIFO must be controlled to accommodate for non-uniformity and variations in the incoming data rate so that a sufficiently smooth output data stream may be produced during normal operating conditions. In addition FIFO overflow and underflow must be prevented in extreme operating conditions. It is found that a PLL controller of the type outlined above is inadequate for producing a data stream which meets the increasing standards required in modern telecommunications networks, particularly in mobile telephone networks.
According to a first aspect of the invention, there is provided an apparatus for controlling the read clock signal rate of a First-In First-Out (FIFO) data memory, the apparatus comprising:
an error detector module, responsive to a change in the quantity of data contained in the FIFO data memory to generate an error signal;
an integrator module, for integrating said error signal, scaled by a first scaling parameter, to generate an integrated error signal;
a control module, responsive to said error signal and to said integrated error signal, for generating a control signal which includes said error signal, scaled by a second scaling parameter, and said integrated error signal;
a read clock rate adjuster module, responsive to said control signal to adjust the rate of the read clock signal,
wherein the control module is arranged to determine a value for at least one of the first and second variable scaling parameters according to the level of the error signal.
Varying the value of the or each scaling parameter in accordance with the level of the absolute error signal, makes the bandwidth of the apparatus dynamic and adaptable to the environment in which it operates. The apparatus becomes more sensitive (increased bandwidth) when the absolute error signal levels are high and this enables it to react quickly to changes in an input data stream to ensure that the FIFO does not overflow or underflow. The apparatus becomes less sensitive (decreased bandwidth) when the level of the error signal is low in order to smooth or filter out sharp changes in the input data stream. The apparatus is thus able to strike a balance between, on the one hand, reacting quickly when necessary and, on the other hand reacting more slowly, or smoothly, when possible.
In a preferred embodiment of the invention, the control module is arranged such that the or each determined scaling parameter value varies at a rate which increases as the absolute error signal level increases, and decreases as the absolute error signal level decreases. It is particularly preferred that the control module is arranged such that the or each determined scaling parameter value varies substantially in accordance with an exponential function of the absolute error signal level. The resulting response characteristics of the apparatus enable it to meet relatively stringent wander and jitter specifications while still preventing FIFO overflow and underflow.
Preferably, the control module is arranged to calculate the value of at least one of the first and second scaling parameters by application of a mathematical function to the absolute error signal level. Alternatively, the value is derived from a data array.
Preferably, the error signal is derived from the difference between a read address pointer of the FIFO data memory and a write address pointer of the FIFO data memory.
Preferably, the error signal comprises a series of discrete error values and the integrator module is arranged to perform a summation operation on the error values, the error values first having been scaled by said first scaling parameter. Advantageously, a data processor is used to implement the error detector module, the integrator module and the control module.
In a preferred embodiment, the read clock adjuster module is arranged to operate on a primary clock signal and comprises a first counter for dividing the primary clock signal to generate a nominal read clock signal. The read clock adjuster module is further arranged to add one or more primary clock cycles to one or more of the respective nominal primary clock cycle numbers when the control signal indicates that the read clock signal rate is to be decreased, and to subtract one or more primary clock cycles when the read clock signal rate is to be increased. Preferably, the number of primary clock cycles to which a cycle of the read clock signal corresponds is determined in accordance with a cycle pattern and the apparatus further includes a pattern selector module arranged to select one of a number of different cycle patterns depending on whether it is desired to speed up or slow down the read clock signal rate.
A second aspect of the invention provides a method of controlling the read clock signal rate of a First-In First-Out (FIFO) data memory, the method comprising:
generating an error signal responsive to a change in the quantity of data stored in the FIFO data memory;
generating an integrated error signal by performing an integration operation on said error signal scaled by a first scaling parameter;
generating a control signal which includes said error signal, scaled by a second scaling parameter, and said integrated error signal;
determining a value for at least one of said first or second scaling parameters according to the level of the error signal;
adjusting the read clock signal rate according to said control signal.
A third aspect of the invention provides a desynchronising apparatus for a telecommunications network system, the apparatus being arranged to receive an input data stream which comprises plesiochronous data elements decoded from a synchronous transmission format, and to produce an output data stream, comprising plesiochronous data elements, at a substantially constant frequency the desynchronising apparatus comprising an apparatus according to the first aspect of the invention.
A fourth aspect of the invention provides a method of controlling the read clock signal rate of a First-In First-Out data memory in a desynchronising apparatus according to the third aspect of the invention.
A fifth aspect of the invention provides a telecommunications network node including the apparatus of the first aspect of the invention.
Other aspects of the present invention will become apparent to those ordinary skilled in the art upon review of the following description of specific embodiments of the invention and with reference to the accompanying drawings.